When transmitting data between a sender and a receiver, the problem generally arises that the internal clock of the receiver has to be synchronized with the internal clock of the sender so as to provide a satisfactory data transmission. Otherwise, the transmitted data is sampled by a sampling device of the receiver at bad points in time, resulting in transmission errors. It should be noted that the stated problem arises for any sender/receiver combination having independent internal clocks, regardless of the physics of the transmission channel. This means that the problem equally arises for transmitting data by use of sound, light, radio waves and any other medium.
To provide satisfactory synchronization and data transmission, a digital input signal is therefore sampled by a sampling device at a sampling frequency which is significantly higher than the frequency of the digital signal. Hence, the receiver comprises a clock generation device, which generates a clock signal with an appropriate frequency. However, generating a clock signal with a relatively high frequency unfortunately results in a relatively high power consumption.
Several methods have been found in the prior art to provide clock signals having such a high frequency. One example is a quartz oscillator. A further example is U.S. Pat. No. 6,388,492 B2, which discloses a clock generation circuit including a multiphase clock generation circuit for generating multiphase clocks of a predetermined frequency, pulse generation circuits for generating a plurality of non-overlap pulses by using at least a part of the multiphase clocks, and a circuit for obtaining an OR of the plurality of non-overlap pulses, thereby generating a clock not having a simple whole multiple ratio relationship with respect to a frequency of the multiphase clocks or a clock having a higher frequency without causing an increase of power consumption and an increase of chip area. Thus, a clock having a frequency which is different from that of the multiphase clocks is generated.